A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large scale integration has resulted in continued shrinking of device and circuit dimensions and features. In integrated circuits having field-effect transistors, for example, one very important process step is the formation of the gate for each of the transistors, and in particular the dimensions of the gate. In many applications, the performance characteristics (e.g., switching speed) and size of the transistor are functions of the size (e.g., width) of the transistor's gate. Thus, for example, a narrower gate tends to produce a higher performance transistor (e.g., faster) that is inherently smaller in size (e.g., narrower width).
To pattern narrower transistor gates, a bottom anti-reflective coating (BARC) is often added between a gate material layer and a resist layer to reduce reflected waves during the patterning of the resist layer. Once the transistor gate has been formed and the remaining portions of the resist layer (i.e., the resist mask) have been stripped away, there is a need to remove the remaining portions of the BARC that are over the transistor's gate.
Inorganic BARC materials can be difficult to remove, and the removal process can result in damage to other materials. For example, if the BARC is made of silicon oxynitride, prior art BARC removal methods typically require using an HF acid dip to remove oxidized portions of the silicon oxynitride followed by a hot phosphoric acid strip. Unfortunately, the HF dip process can attack and damage exposed silicon dioxide.
Thus, there is a need for improved and more efficient methods for removing the BARC without requiring a HF dip process, which can damage the semiconductor wafer.